Basics of Computer Organisation

L 3 C 3

Teachers Continuous Evaluation: as per university examination norms. End Term Theory Examination: as per university examination norms.

Course outcomes

• Understand number systems, Boolean algebra, and design basic combinational and sequential logic circuits.[K2]
• Analyze and design digital components such as adders, multiplexers, flip-flops, and counters used in CPUs.[K4]
• Describe the structure and functioning of a computer system including instruction sets, CPU, memory, and I/O. [K2]
• Evaluate memory organization and performance enhancement techniques like pipelining and caching.[K5]

Unit I (8 lectures)

Digital Logic Fundamentals Number Systems & Codes: Binary, octal, decimal, hexadecimal, Signed numbers: 1’s and 2’s complement, BCD, ASCII, Gray code. Boolean Algebra and Logic Gates: Postulates and theorems, Truth tables, Basic and universal logic gates, SOP and POS forms, Karnaugh Maps (K-Map) for 2 to 4 variables. Combinational Logic Design: Adders (Half, Full), Subtractors, Multiplexers, Demultiplexers, Encoders, Decoders, Comparators.

Unit II (8 lectures)

Sequential Logic & Digital Building Blocks Sequential Logic Basics: Flip-Flops (SR, D, T, JK) – operation and timing, Registers, Shift registers, Counters – asynchronous and synchronous. Memory Elements: Basics of RAM, ROM, PROM, EPROM, Static vs Dynamic RAM, Timing diagrams and read/write operations. CPU Control Logic Introduction: Difference between combinational and sequential circuits, Concept of FSM (Finite State Machines), Brief introduction to control logic in CPU.

Unit III (8 lectures)

Computer Organisation & I/O Systems Basic Functional Blocks of a Computer: CPU, memory, I/O subsystems, control unit, Instruction execution cycle, RTL interpretation, Addressing modes and instruction set architecture, I/O System Organisation: Program-controlled, interrupt-driven and DMA, Peripheral devices: characteristics and interfacing, Privileged vs non-privileged instructions, Software interrupts, traps, and process transitions

Unit IV (8 lectures)

Advanced Memory and Performance Techniques Performance Enhancement Techniques: Pipelining: basic concepts, stages, Pipeline hazards: structural, data, and control, Throughput and speedup Memory Hierarchy: Cache memory: mapping techniques – direct, associative, set-associative, Cache replacement policies: FIFO, LRU, random, Write policies: write-through and write-back, Memory interleaving, Concept of hierarchical memory organisation

Textbooks

• Mano, M. M. (2007). Computer system architecture (3rd ed.). Prentice Hall of India.
• Hamacher, C., Vranesic, Z. G., & Zaky, S. G. (2002). Computer organization (5th ed.). McGraw-Hill.
• Patterson, D. A., & Hennessy, J. L. (2020). Computer organization and design: The hardware/software interface (6th ed.).

References

• Stallings, W. (2006). Computer organization and architecture: Designing for performance (7th ed.). Pearson/Prentice Hall.
• Gaonkar, R. S. (2002). Microprocessor architecture, programming, and applications with the 8085 (5th ed.). Prentice Hall.
• Carpinelli, J. D. (2001). Computer systems organization and architecture. Pearson Education.
• Hennessy, J. L., & Patterson, D. A. (2019). Computer architecture: A quantitative approach (6th ed.). Morgan Kaufmann.
• Roth, C. H., Jr., & Kinney, L. L. (2020). Fundamentals of logic design (8th ed.). Cengage Learning.